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Espressif Systems /ESP32-S3 /EXTMEM /CORE1_DBUS_REJECT_ST

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Interpret as CORE1_DBUS_REJECT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CORE1_DBUS_TAG_ATTR 0CORE1_DBUS_ATTR 0 (CORE1_DBUS_WORLD)CORE1_DBUS_WORLD

Description

******* Description ***********

Fields

CORE1_DBUS_TAG_ATTR

The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.
CORE1_DBUS_ATTR

The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.
CORE1_DBUS_WORLD

The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1

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Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data